When planning a layout for an integrated circuit, high-level hardware modeling software tools are often used. A high-level modeling system (HLMS) provides a high-level abstraction of low-level hardware components and intellectual property (IP) cores to be implemented in an integrated circuit. Accordingly, such tools allow electronic designs to be described and simulated in a high-level modeling environment. High-level models generated by an HLMS can then be automatically translated into corresponding low-level hardware implementations.
Unlike design approaches using a traditional hardware description language (HDL) representation of a circuit design, users instantiate high-level modeling blocks and wire them in an HLMS to properly construct a target integrated circuit device. Many HLMS-based design tools provide mechanisms such as automatic rate-and-type propagation, high-level resource estimation and timing analysis tools to facilitate the modeling process.
An HLMS-based design tool generally enables users to more quickly implement a circuit design. More particularly, an HLMS tool provides an efficient layout of a circuit design using circuit elements of the device in which the circuit design is to be implemented. However, conventional HLMS-based design tools have a number of limitations.